Publikationen

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2022

  • P. Sittel, N. Fiege, J. Wickerson, and P. Zipf, “Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 3, pp. 614–627, Mar. 2022, doi: 10.1109/TCAD.2021.3060320.
  • N. Fiege, P. Sittel, and P. Zipf, “Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling,” in 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2022, pp. 1–2. doi: 10.1109/FCCM53951.2022.9786117.
     

2021

  • Botache, Diego and Bethke, Florian and Hardieck, Martin and Bieshaar, Maarten and Brabetz, Ludwig and Ayeb, Mohamed and Zipf, Peter and Sick, Bernhardet,  “Towards Highly Automated Machine-Learning-Empowered Monitoring of Motor Test Stands,” in 2021 IEEE International Conference on Autonomic Computing and Self-Organizing Systems (ACSOS), 2021, pp. 120–130.

2020

  • P. Sittel, J. Wickerson, M. Kumm, and P. Zipf, “Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design,” in 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2020, pp. 568–573. doi: 10.1109/ASP-DAC47756.2020.9045616.
  • Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, and Philip H. W. Leong: "AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems. doi: doi.org/10.1109/TVLSI.2019.2939429

2019

  • Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan Moss, Peter Zipf, and Philip H. W. Leong. 2019. Unrolling Ternary Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 12, 4, Article 22 (October 2019), 23 pages. DOI: doi.org/10.1145/3359983
  • Patrick Sittel, Nicolai Fiege, Martin Kumm and Peter Zipf: Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling, Accepted for presentation at: International Conference on Reconfigurable Computing and FPGAs, Cancun, December 2019.
  • Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees Vissers. Efficient Error-Tolerant Quantized Neural Network Accelerators. 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Noordwijk, Netherlands, 2019, pp. 1-6, doi: doi.org/10.1109/DFT.2019.8875314. Received the best paper award!
  • Julian Oppermann, Patrick Sittel, Martin Kumm, Melanie Reuter-Oppermann, Andreas Koch and Oliver Sinnen Design-Space Exploration with Multi-Objective Resource Aware Modulo Scheduling, in 25th International Conference on Parallel and Distributed Computing (Euro-Par), Göttingen, August 2019. doi: doi.org/10.1007/978-3-030-29400-7_13
  • M. Garrido, K. Möller and M. Kumm, World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 4, pp. 1507-1516, April 2019. doi: doi.org/10.1109/TCSI.2018.2886626
  • Martin Hardieck, Martin Kumm, Konrad Möller, and Peter Zipf. 2019. Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '19). ACM, New York, NY, USA, 43-52. DOI: doi.org/10.1145/3289602.3293905

2018

  • Martin Hardieck, Martin Kumm, Patrick Sittel and Peter Zipf: Constant Matrix Multiplication with Ternary Adders, 25th IEEE International Conference on Circuits and Systems (ICECS), Bordeaux December 2018, pp. 85-88. DOI: doi.org/10.1109/ICECS.2018.8617860
  • Patrick Sittel, Julian Oppermann, Martin Kumm, Andreas Koch and Peter Zipf: HatScheT: A Contribution to Agile HLS, In: 5th Workshop on FPGAs for Software Programmers (FSP), Dublin August 2018 (preprint).
  • Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch: ILP-based Modulo Scheduling and Binding for Register Minimization, In 28th International Conference on Field Programmable Logic and Application (FPL), Dublin August 2018 (preprint).
  • Martin Kumm, Oscar Gustafson, Florent de Dinechin, Johannes Kappauf and Peter Zipf, Karatsuba with Rectangular Multipliers for FPGAs, IEEE Symposium on Computer Arithmetic (ARITH), 2018, received the best paper award!
  • Martin Kumm: Optimal Constant Multiplication using Integer Linear Programming, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 65, Issue 5, May 2018, (preprint, copyright IEEE), DOI.
  • Konrad Möller, Martin Kumm, Mario Garrido, Peter Zipf: Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits.In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 37, Issue: 3, p710-714, March 2018, 10.1109/TCAD.2017.2729467
  • Patrick Sittel, Thomas Schönwälder, Martin Kumm  and Peter Zipf: ScaLP: A Light-Weighted (MI)LP-Library,  21. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), March 2018, Tübingen (preprint).
  • Martin Kumm and Johannes Kappauf: Advanced Compressor Tree Synthesis for FPGAs, IEEE Transactions on Computers, Volume 67, Issue 8, Aug. 2018, (preprint, copyright IEEE), DOI.
  • Martin Kumm, Oscar Gustafsson, Mario Garrido and Peter Zipf: Optimal Single Constant Multiplication using Ternary Adders, IEEE Transactions on Circuits and Systems-II: Express Briefs, Volume 65, Issue 7, July 2018 (http://doi.org/10.1109/TCSII.2016.2631630)

2017

  • Patrick Sittel, Martin Kumm, Konrad Möller, Peter Zipf, Bogdan Pasca and Mark Jervis: Model-Based Hardware Design based on Compatible Sets of Isomorphic Subgraphs,  In: International Conference on Field Programmable Technology (ICFPT), 11-13 Dec. 2017, 10.1109/FPT.2017.8280140.
  • Konrad Möller: Run-time Reconfigurable Constant Multiplication on Field Programmable Gate Arrays Dissertation, Defended: 11.08.2017, kassel university press, ISBN: 978-3-7376-0376-8 (online/print)
  • Dieter Lens, Martin Hardieck, Kerstin Groß, Harald Klingbeil, Martin Kumm, Konrad Möller, Peter Zipf: Signal processing development for the SIS100 bunch-by-bunch longitudinal feedback In: Scientific Report 2016, vol. 2017, Darmstadt: GSI Helmholtzzentrum für Schwerionenforschung, 2017, 486 p. 
  • Martin Kumm, Johannes Kappauf, Matei Istoan and Peter Zipf: Resource Optimal Design of Large Multipliers for FPGAs. IEEE Symposium on Computer Arithmetic (ARITH), 2017, preprint
  • Martin Kumm, Martin Hardieck and Peter Zipf: Optimization of Constant Matrix Multiplication with Low Power and High Throughput, IEEE Transaction on Computers, Volume 66, Issue 12, 2017, https://doi.org/10.1109/TC.2017.2701365, preprint
  • Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck  and Peter Zipf:
  • High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits, In: 20. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 103-113, Shaker Verlag, ISBN: 978-3-8440-4996-1, 2017, preprint
  • Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf: Reconfigurable Constant Multiplication for FPGAs, In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 6, pp. 927-937, 2017, http://dx.doi.org/10.1109/TCAD.2016.2614775

2016

  • Martin Kumm, Peter Zipf: Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs” International Journal of Reconfigurable Computing, 2016, Article ID 3015403, (http://dx.doi.org/10.1155/2016/3015403, open access)
  • Martin Kumm, Marco Kleinlein, Peter Zipf: Efficient Sum of Absolute Difference Computation on FPGAs, IEEE International Conference on Field Programmable Logic and Application (FPL) 2016, Lausanne (preprint, copyright IEEE)
  • Uwe Meyer-Baese, Harikrishna Muddu, Sebastian Schinhaerl, Martin Kumm, Peter Zipf: Real-time Fetal ECG System Design using Embedded Microprocessors In: Proc. SPIE Commercial + Scientific Sensing and Imaging. Editors:  Liyi Dai, Yufeng Zheng, Henry Chu, A. Meyer-Baese; April 2016, Vol. 9871, pp.  987106-1-14, http://doi.org/10.1117/12.2224256
  • Eugen Bayer: Entwurf und Systemintegration eines Signalsyntheseverfahrens auf programmierbaren Logikbausteinen Dissertation, Defended: 15.01.2016, kassel university press, ISBN: 978-3-7376-5015-1, 2016

2015

  • Martin Kumm: Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays Dissertation, Defended: 30.10.2015, Published: 02.05.2016, Springer Wiesbaden, ISBN: 978-3-658-13322-1, http://doi.org/10.1007/978-3-658-13323-8 (in case you don't have access, ask for preprints)
  • Mario Garrido, Petter Källström, Martin Kumm and Oscar Gustafson: CORDIC II: A New Improved CORDIC Algorithm In: IEEE Transactions on Circuits and Systems II: Express Briefs, 63(2), 186–190. 2016, http://doi.org/10.1109/TCSII.2015.2483422
  • Konrad Möller, Martin Kumm, Charles-Frederic Müller, Peter Zipf: Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits In: FPGAs for Software Programmers (FSP), 2015, arXiv:1508.06811 (preprint), Link to Benchmarks
  • Mathias Faust, Martin Kumm, Chip-Hong Chang and Peter Zipf: Efficient Structural Adder Pipelining in Transposed Form FIR Filters In: 20th International Conference on Digital Signal Processing (DSP 2015), 2015 (preprint, copyright IEEE, http://dx.doi.org/10.1109/ICDSP.2015.7251882)
  • Martin Kumm, Shahid Abbas and Peter Zipf: An Efficient Softcore Multiplier Architecture for Xilinx FPGAs In: 22nd IEEE Symposium on Computer Arithmetic (ARITH 22), 2015 (preprint, copyright IEEE, http://dx.doi.org/10.1109/ARITH.2015.17)

2014

  • Konrad Möller, Martin Kumm, Peter Zipf, Kerstin Groß, Dieter Lens, and Harald Klingbeil:
    FPGA Based Tunable Digital Filtering for Closed Loop RF Control in Synchrotrons,
    In: Scientific Report 2013, vol. 2014, Darmstadt: GSI Helmholtzzentrum für Schwerionenforschung, 2014 (pdf, copyright GSI)
  • Martin Kumm and Peter Zipf:
    Pipelined Compressor Tree Optimization using Integer Linear Programming
    In: International Conference on Field Programmable Logic and Application (FPL), 2014 (preprint, copyright IEEE, http://dx.doi.org/10.1109/FPL.2014.6927468)
  • M. Kunz, A. Ostrowski and P. Zipf: An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications, 2014 24th International Conference on Field Programmable Logic and Applications (FPL), Munich, 2014, pp. 1-4.; (http://dx.doi.org/10.1109/FPL.2014.6927406)
  • Konrad Möller, Martin Kumm, Marco Kleinlein and Peter Zipf:
    Pipelined Reconfigurable Multiplication with Constants on FPGAs
    In: International Conference on Field Programmable Logic and Application (FPL), 2014 (preprint, copyright IEEE, http://dx.doi.org/10.1109/FPL.2014.6927466)
  • Konrad Möller, Martin Kumm, Björn Barschtipan and Peter Zipf: 
    Dynamically Reconfigurable Constant Multiplication on FPGAs
    In: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Cuvillier, ISBN: 978-3-95404-637-9, 2014 (preprint, copyright Cuvillier Verlag)
  • Martin Kumm, Peter Zipf:
    Efficient High Speed Compression Trees on Xilinx FPGAs
    In: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Cuvillier, ISBN: 978-3-95404-637-9, 2014 (preprint, copyright Cuvillier Verlag)

2013

  • Tze Ying Sim, Sian Lun Lau, Peter Zipf, Kevin Kimm:
    Design And Development Of A Supported Tiered Software For Teaching And Learning Using A Connected Mobile Learning Application
    In: Innovation Challenges in Multidisciplinary Research & Practice (ICMRP 2013), Kuala Lumpur, p.     151 (Abstract)
  • Eugen Bayer, Peter Zipf, Alexander Klaus, Harald Klingbeil, Gerald Schreiber:
    Fast FPGA Based Low-Trigger-Jitter Waveform Generator Method for Barrier-Bucket Electronics at FAIR,
    Poster, p. 1352, 2013 North American Particle Accelerator Conference (NA-PAC’13),Pasadena, California, 29.Sep-4.Oct 2013
  • Martin Kumm, Konrad Möller and Peter Zipf:
    Dynamically Reconfigurable FIR Filter Architectures with Fast Reconfiguration
    In: 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2013 (DOI or preprint, copyright IEEE)
  • Martin Kumm, Martin Hardieck,  Jens Willkomm, Peter Zipf and Uwe Meyer-Baese: 
    Multiple Constant Multiplication with Ternary Adders
    In: International Conference on Field Programmable Logic and Application (FPL), 2013 (DOI or preprint, copyright IEEE)
  • Martin Kumm, Diana Fanghänel, Konrad Möller, Peter Zipf and Uwe Meyer-Baese:
    FIR Filter Optimization for Video Processing on FPGAs
    In: EURASIP Journal on Advances in Signal Processing, Springer, 2013 (DOI open access)
  • Martin Kumm, Konrad Möller and Peter Zipf:
    Reconfigurable FIR Filter Using Distributed Arithmetic on FPGAs
    In: Circuits and Systems, International Symposium on (ISCAS), 2013 (DOI or preprint, copyright IEEE)
  • Martin Kumm, Konrad Möller and Peter Zipf:
    Partial LUT Size Analysis in Distributed Arithmetic FIR Filters on FPGAs
    In: Circuits and Systems, International Symposium on (ISCAS), 2013 (DOI or preprint, copyright IEEE)

2012

  • Martin Kumm and Peter Zipf:
    Hybrid Multiple Constant Multiplication for FPGAs
    In: Electronics, Circuits and Systems, International Conference On (ICECS)  2012
    (DOI or preprint, copyright IEEE)
  • Martin Kumm and Katharina Liebisch and Peter Zipf:
    Reduced Complexity Single and Multiple Constant Multiplication in Floating Point Precision
    In: Field Programmable Logic and Applications,  International Conference on (FPL) 2012 
    (DOI or preprint, copyright IEEE)
  • Michael Kunz and Martin Kumm and Martin Heide and Peter Zipf
    Area Estimation of Look-Up Table based Fixed-Point Computations on the example of a Real-Time High Dynamic Range Imaging System
    In: Field Programmable Logic and Applications,  International Conference on (FPL) 2012 
    (DOI or preprint, copyright IEEE)
  • Uwe Meyer-Baese and Guillermo Botella and David E. T. Romero and Martin Kumm:
    Optimization of high speed pipelining in FPGA-based FIR filter design using genetic algorithm 
    In: Proceedings of SPIE 2012 (Vol. 8401)
    (DOI, please ask for preprint)
  • Martin Kumm and MathiasFaust and Peter Zipf and Chip-Hong Chang: Pipelined Adder Graph Optimization for High Speed Multiple Constant Multiplication. 
    In: Circuits and Systems, International Symposium on (ISCAS) 2012.
    (DOI or preprint, copyright IEEE)

2011

  • Martin Kumm and Peter Zipf:
    High Speed Low Complexity FPGA-based FIR Filters Using Pipelined Adder Graphs.
    In: Field Programmable Technology, International Conference on (ICFPT), 12-14 Dec. 2011, pp. 1-4 
    (DOI or preprint, copyright IEEE)
  • Bayer, E.; Zipf, P.; Traxler, M.;:
    A multichannel high-resolution (<5 ps RMS between two channels) Time-to-Digital Converter (TDC) implemented in a field programmable gate array (FPGA), In: Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE , pp. 876-879, 23-29 Oct. 2011
    (DOI)

2010

  • Martin Kumm, Harald Klingbeil, Peter Zipf:
    An FPGA-Based Linear All-Digital Phase-Locked Loop,
    IEEE Transactions on Circuits an Systems-I: Regular Papers, 2010, pp. 2487-2497
    (DOI or preprint, copyright IEEE)

2009

  • Chau, T.C.P. and Ho, S.M.H. and Leong, P.H.W. and Zipf, P. and Glesner, M.:
    Generation of Synthetic Floating-Point benchmark circuits,
    IEEE International Symposium on Parallel Distributed Processing, 2009, IPDPS 2009, pp. 1-9, doi:10.1109/IPDPS.2009.5161203
  • Yu, H. and Leong, P.H.W. and Hinkelmann, H. and Möller, L. and Glesner, M. and Zipf, P.:
    Towards a unique FPGA-based identification circuit using process variations,
    International Conference on Field Programmable Logic and Applications, 2009, FPL 2009, pp. 397-402, doi:10.1109/FPL.2009.5272255
  • Hinkelmann, H. and Zipf, P. and Glesner, M.:
    Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes,
    International Conference on Field Programmable Logic and Applications, 2009, FPL 2009, pp. 359-366, doi:10.1109/FPL.2009.5272268
  • Rullmann, M. and Merker, R. and Hinkelmann, H. and Zipf, P. and Glesner, M.:
    An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs,
    International Conference on Field Programmable Logic and Applications, 2009. FPL 2009, pp. 92-98, doi:10.1109/FPL.2009.5272540
  • Heiko Hinkelmann, Peter Zipf, Jia Li, Guifang Liu, Manfred Glesner:
    On the design of reconfigurable multipliers for integer and Galois field multiplication,
    Microprocessors and Microsystems, Volume 33, Issue 1, February 2009, pp. 2-12, Selected papers from ReCoSoC 2007, Elsevier
  • Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, and Manfred Glesner:
    A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips,
    International Journal of Reconfigurable Computing, vol. 2009, Article ID 453970, 14 pages, 2009. doi:10.1155/2009/453970

2008

  • Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
    A Scalable Reconfiguration Mechanism for Fast Dynamic Reconfiguration,
    International Conference on ICECE Technology, 2008. FPT 2008, pp. 145-152, December 7-10, Taipei, Taiwan, 2008
  • Peter Zipf, Heiko Hinkelmann, Hui Shao, Radu Dogaru, Manfred Glesner:
    An Area-Efficient Realisation of a Codebook-Based Image Compression Mathod,
    International Conference on ICECE Technology, 2008. FPT 2008, pp. 349-352, December 7-10, Taipei, Taiwan, 2008
  • Hinkelmann, H. and Zipf, P. and Glesner, M. and Alles, M. and Vogt, T. and Wehn, N. and Kappen, G. and Noll, T.G.:
    SPP1148 booth: Application-specific reconfigurable processors,
    International Conference on Field Programmable Logic and Applications, 2008. FPL 2008, p. 350
  • Eisenhardt, S. and Schweizer, T. and de Oliveira Filho, J.A. and Oppold, T. and Rosenstiel, W. and Thomas, A. and Becker, J. and Hannig, F. and Kissler, D. and Dutta, H. and Teich, J. and Hinkelmann, H. and Zipf, P. and Glesner, M.:
    SPP1148 booth: Coarse-grained reconfiguration,
    International Conference on Field Programmable Logic and Applications, 2008. FPL 2008, p. 349
  • Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner:
    A Decentralised Task Mapping Approach for Homogeneous Multi-Processor Network-on-Chips,
    in ReCoSoC'08, July 9-11, Barcelona, Spain, 2008
  • Christopher Spies, Peter Zipf, Manfred Glesner, Harald Klingbeil:
    Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II,
    IFIP/IEEE Symposium on Rapid System Prototyping (RSP), pp. 196-202, Monterey, CA, June 2-5, 2008
  • Peter Zipf:
    Applying Dynamic Reconfiguration for Fault Tolerance in Fine-grained Logic Arrays,
    Transactions on Very Large Scale Integration (VLSI) Systems, 16(2): 134-143, Feb. 2008
  • Martin Kumm, Shahab Sanjari:
    Digital Hilbert Transformers for FPGA-based Phase-Locked Loops,
    International Conference on Field Programmable Logic and Applications, 2008. FPL 2008, p. 251 
    (DOI or preprint, copyright IEEE)

2007

  • Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
    A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks,
    in Proceedings of the International Conference on Field-Programmable Technology (ICFPT), pp. 313-316, Kokurakita, Kitakyushu, Japan, December 12-14, 2007
  • Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, and Tobias G. Noll:
    A Power Estimation Model for an FPGA-based Softcore Processor,
    in 17th International Conference on Field Programmable Logic and Applications (FPL'07), pp. 171-176, August, 2007
  • Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner:
    A Customizable LEON2-Based VLIW Processor,
    in ReCoSoC'07, June 18-20, Montpellier, France, 2007
  • Heiko Hinkelmann, Tudor Murgan, Guifang Liu, Peter Zipf, Manfred Glesner:
    On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication,
    in ReCoSoC'07, June 18-20, Montpellier, France, 2007
  • H. Hinkelmann, P. Zipf, M. Glesner, and T. Pionteck:
    Dynamically Reconfigurable Computing for Wireless Communication Systems,
    in "it - Methods and Applications of Informatics and Information Technology", 3/2007, pp. 174-180, Oldenbourg Wissenschaftsverlag, 2007
  • M. Glesner, T. Murgan, T. Hollstein, P. Zipf, O. Soffke, and H. Hinkelmann:
    System Design Challenges in the Nanoscale Era,
    in Scientific Bulletin of the Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology - Information Technology Series, vol 12, pp. 3-14, Gdansk, Poland, 2007
  • Peter Zipf, Lei Liu, Zdravko Bozakov, Manfred Glesner:
    Design Optimisations for a Cellular Automata Model with Programmable Interconnect Structure,
    in Workshop on Dynamically Reconfigurable Systems (DRS), pp. 123-132, Zurich, 15 March, 2007
  • Peter Zipf, Yang Qiao, Manfred Glesner:
    Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen,
    in 10. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pp. 253-262, Erlangen, 5-7 März, 2007

2006

  • Marcos Aurelio Belchior, Kyra Wulffert, Peter Zipf, Manfred Glesner:
    Simulated Annealing Algorithms for Optimal Packet Scheduling in Ad Hoc Networks,
    The International Conference on Software, Telecommunications and Computer Networks (SoftCOM'06), pp. 142-146, Split - Dubrovnik, Croatia, September 29 - October 1, 2006
  • Oliver Soffke, Peter Zipf, Michael Velten, Manfred Glesner:
    Simulation von CNFET basierten Digitalschaltungen,
    Journal: Advances in Radio Science - Kleinheubacher Berichte, Vol. 4, 2006, pp. 307-311, ISSN: 16849965, Copernicus GmbH (Publisher)
  • Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner:
    Multitasking Support for Dynamically Reconfigurable Systems,
    In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL'06), pp. 219-224, Madrid, Spain, August 28-30, 2006
  • Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
    A Concept for a Profile-based Dynamic Reconfiguration Mechanism,
    In Reconfigurable Communication-centric SoCs (ReCoSoC'06), Montpellier, France, July 3-5, 2006
  • Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
    Design Concepts for a Dynamically Reconfigurable Wireless Sensor Node,
    In Proceedings of the 1st NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2006), pp. 436-441, Istanbul, Turkey, June 15-18, 2006
  • Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
    A metric for the energy-efficiency of dynamically reconfigurable systems,
    In 19th International Conference on Architecture of Computing Systems (ARCS'06), Workshop on Dynamically Reconfigurable Systems, pp. 152-161, Frankfurt/Main, 13.-16. March, 2006
  • Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, and Manfred Glesner:
    Implementation of Realtime and Highspeed Phase Detector on FPGA,
    In International Workshop On Applied Reconfigurable Computing (ARC2006), pp. 1-11, Delft, The Netherlands, March 1-3, 2006
  • Peter Zipf, Volker Hampel, Manfred Glesner, and Thilo Pionteck:
    Eine Scheduling Heuristik zur Minimierung der Verlustleistung,
    9. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pp. 51-60, Dresden, 20.-22. Februar, 2006
  • O. Soffke, P. Zipf, T. Murgan, and M. Glesner:
    A Signal Theory Based Approach to the Statistical Analysis of Combinatorial Nanoelectronic Circuits,
    In Proc. of Design, Automation and Test in Europe (DATE) Conf., pp. 632-637, Munich, Germany, 6-10 March, 2006

2005

  • Soffke, O.; Zipf, P.; Glesner, M.:
    Simulation von CNFET basierten Digitalschaltungen,
    Proceedings of Kleinheubacher Tagung, Kleinheubach, September 26-30, 2005
  • Peter Zipf, Oliver Soffke, Michael Velten, Manfred Glesner:
    Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC,
    Workshop Entwurfsmethoden für Nanometer VLSI Design, pp. 329-333, Informatik LIVE 2005, 19-22 September, Bonn, 2005
  • P. Zipf, O. Soffke, A. Schumacher, C. Schlachta, R. Dogaru, and M. Glesner:
    A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata,
    15th International Conference on Field Programmable Logic and Applications (FPL'05), pp. 335-340, August 24-26, Tampere, Finland, 2005
  • P. Zipf, O. Soffke, A. Schumacher, R. Dogaru, and M. Glesner:
    Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata,
    15th International Conference on Field Programmable Logic and Applications (FPL'05), pp. 329-334, August 24-26, Tampere, Finland, 2005
  • S. Cotofana, A. Schmid, Y. Leblebici, A. Ionescu, O. Soffke, P. Zipf, M. Glesner, and A. Rubio:
    CONAN - A Design Exploration Framework for Reliable Nano-Electronics Architectures,
    IEEE 16th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2005), pp. 260-267, July 23-25, Samos, Greece, 2005
  • M. Glesner, H. Hinkelmann, T. Hollstein, L.S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, and P. Zipf:
    Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques,
    The 5th International Workshop on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS V), pp. 12-21, July 18-20, Samos, Greece, 2005
  • Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner:
    On a Hardware Architecture for the Evolution of Cellular Automata Functionality,
    7th International Symposium on Signals, Circuits and Systems (ISSCS'05), pp. 91-94, July 14-15, Iasi, Romania, 2005
  • Peter Zipf, Claude Stötzler, and Manfred Glesner:
    Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model,
    In Reconfigurable Communication-centric SoCs (ReCoSoC) Workshop, Montpellier, France, June 27-29, 2005
  • T. Murgan, A. M. Obeid, A. Guntoro, P. Zipf, M. Glesner, and U. Heinkel:
    Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks,
    In Reconfigurable Communication-centric SoCs (ReCoSoC) Workshop, Montpellier, France, June 27-29, 2005
  • Clemens Schlachta, Oliver Soffke, Peter Zipf, M. Glesner:
    Eine weiterentwickelte quasi-statische adiabatische Logikfamilie,
    35. GI Jahrestagung (1), p. 448, Bonn, 2005
  • M. Petrov, T. Murgan, P. Zipf, M. Glesner:
    Functional Modelling Techniques for a Wireless LAN OFDM Transceiver,
    In IEEE International Symposium on Circuits and Systems (ISCAS'05), pp. 3970-3973, 23-26 May, Kobe, Japan, 2005

2004

  • Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner:
    A Switch Architecture and Signal Synchronization for GALS System-on-Chips,
    In Proc. of 17th Symposium on Integrated Circuits and Systems Design (SBCCI2004), pp. 210-215, Porto de Galinhas, Pernambuco, Brazil, September 7-11, 2004
  • M. Petrov, T. Murgan, F. May, M. Vorbach, P. Zipf, M. Glesner:
    The XPP Architecture and its Co-Simulation within the Simulink Environment,
    In Proc. of the Intl. Conference on Field Programmable Logic and Applications, pp. 761-770, Antwerp, Belgium, August 30 - September 1, 2004
  • Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong Pang Pun, Kuen Hung Tsoi, Kin Hong Lee, Philip Leong:
    IP Generation for an FPGA-based Audio DAC Sigma-Delta Converter,
    In Proc. of the Intl. Conference on Field Programmable Logic and Applications, pp.526-535, Antwerp, Belgium, August 30 - September 1, 2004
  • M. Petrov, T. Murgan, A. Obeid, C. Chitu, P. Zipf, J. Brakensiek, M. Glesner:
    Dynamic Power Optimization of the Trace-Back Process for the Viterbi Algorithm,
    In Proc. of the IEEE Intl. Symposium on Circuits and Systems (ISCAS), pp. II-721-4, Vol 2, Vancouver, Canada, May 23-26, 2004
  • Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner:
    Adaptive Architectures for an OTN Processor: Reducing Design Costs Through Reconfigurability and Multiprocessing,
    Conf. Computing Frontiers, pp. 404-418, Ischia, Italy, April 14-16, 2004
  • Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan:
    Reconfigurable Platforms for Ubiquitous Computing,
    Conf. Computing Frontiers, pp. 377-389, Ischia, Italy, April 14-16, 2004
  • Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Thomas Hollstein, Manfred Glesner:
    An Asynchronous Switch Implementation for Systems-on-a-Chip,
    GI/ITG/GMM Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", pp. 224-231, Feb. 24-25, 2004, Kaiserslautern, Germany (ISBN 3-8322-2486-6)
  • T. Murgan, M. Petrov, M. Majer, Peter Zipf, Manfred Glesner, U. Heinkel:
    Flexible Overhead Processing Architectures for G.709 Optical Transport Networks, Poster,
    GI/ITG/GMM Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", pp. 156-164, Feb. 24-25, 2004, Kaiserslautern, Germany (ISBN 3-8322-2486-6)
  • Peter Zipf, Claude Stötzler, Manfred Glesner:
    A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture,
    IEEE Computer Society annual Symposium on VLSI (ISVLSI), pp. 266-267, Feb. 19-20, 2004, Lafayette, LA, USA.

2003

  • Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner:
    A hierarchical generic approach for on-chip communication, testing and debugging of SoCs,
    IFIP International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC'03), pp. 44-49, Dec. 1-3, 2003, Darmstadt, Germany.
  • S. Bingemer, P. Zipf, M. Glesner:
    An Integrated Model Bridging the Gap between Technology and Economy, Poster Presentation,
    IFIP International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC'03), p. 442, Dec. 1-3, 2003, Darmstadt, Germany.
  • Mihail Petrov, Abdulfattah Obeid, Tudor Murgan, Jörg Brakensiek, Peter Zipf, Manfred Glesner:
    An Adaptive Trace-Back Solution for State-Parallel Viterby Decoders,
    IFIP International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC'03), p. 167, Dec. 1-3, 2003, Darmstadt, Germany.
  • Sujan Pandey, Peter Zipf, Oliver Soffke, Manfred Glesner:
    Ubicomp Device for a Decentralized Distributed Computing Environment,
    In Proc. of the IEEE International Symposium on Signal Processing and Information Technology (ISSPIT'03), pp. 782-785, 14-17 Dec., 2003, Darmstadt.
  • C.H. Ho, K.H. Tsoi, H.C. Yeung, Y.M. Lam, K.H. Lee, P.H.W. Leong, R. Ludewig, P. Zipf, A.G. Ortiz, M. Glesner:
    Arbitrary Function Approximation in HDLs with Application to the N-body Problem,
    Proceedings of the 2003 IEEE International Conference on Field Programmable Technology (FPT), pp. 84-91, December 15-17, 2003, Tokyo, Japan.
  • Sujan Pandey, Peter Zipf, Oliver Soffke, Mihail Petrov, Tudor Murgan, Manfred Glesner, Max Mühlhäuser:
    An Infrastructure for Distributed Computing and Context Aware Computing,
    Workshop: Multi-Device Interfaces for Ubiquitous Peripheral Interaction, at the Fifth International Conference on Ubiquitous Computing, October 12-15, 2003, Seattle, Washington
  • T. Murgan, M. Petrov, A Garcia Ortiz, R. Ludewig, P. Zipf, T. Hollstein, M. Glesner, B. Oelkrug and J. Brakensiek:
    Evaluation and Run-Time Optimisation of On-Chip Communication Structures in Reconfigurable Architectures,
    Intl. Conference on Field Programmable Logic and Applications, pp. 1111-1114, Lisbon, Portugal, 1-3 September 2003
  • S. Bingemer, P. Zipf, M. Glesner:
    A Granularity-based Classification Model for Systems-on-a-Chip, Poster Presentation,
    ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays (FPGA'03), p. 239, 23-25 Feb. 2003, Monterey, California, USA

2002

  • P. Zipf, M. Glesner, C. Bauer, H. Wojtkowiak:
    Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension,
    Proceedings of the 12th International Conference on Field-Programmable Logic and Applications, pp. 586-595, 2-4 Sep. 2002, Montpellier, France
  • C.H. Ho, P.H.W. Leong, K.H. Tsoi, R. Ludewig, P. Zipf, A.G. Ortiz, M. Glesner:
    Fly - A Modifiable Hardware Compiler,
    Proceedings of the 12th International Conference on Field-Programmable Logic and Applications, pp. 381-390, 2-4 Sep. 2002, Montpellier, France
  • T. Pionteck, P. Zipf, L.D. Kabulepa, M. Glesner:
    A Framework for Teaching (Re)Configurable Architectures in Student Projects,
    Proceedings of the 12th International Conference on Field-Programmable Logic and Applications, pp. 444-451, 2-4 Sep. 2002, Montpellier, France
  • M. Glesner, L. Kabulepa, T. Pionteck, O. Mitrea, J. Ocampo Hidalgo, P. Zipf:
    Integration Monolitischer CMOS Schaltungen für Mobilfunkanwendungen: Entwurfsmethoden und Herausforderungen,
    Thema Forschung, (1): pp. 90-95, 2002. ISSN1434-7768.

2000

  • C. Bauer, P. Zipf, H. Wojtkowiak:
    System Design with Genetic Algorithms,
    10th International Conference on Field-Programmable Logic and Applications, pp. 250-259, Villach, Austria, August 2000
  • C. Bauer, P. Zipf, H. Wojtkowiak:
    Integration von Fehlertoleranz im Codesign,
    ITG/GI/GMM Workshop - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, pp. ???-???, 28. Feb. - 1. März, Frankfurt/Main, 2000.
  • P. Zipf, C. Bauer, H. Wojtkowiak:
    A Hardware Extension to Improve Fault Handling in FPGA-Based Systems,
    In Proc. Design and Diagnostics of Electronic Circuits and Systems Workshop, pp. 233-236, Smolenice, Slowakia, 5-7 April 2000.

1999

  • C. Bauer, P. Zipf, H. Wojtkowiak:
    Fault Tolerance with Genetic Algorithms in Hardware Software Codesign
    in Christian Siemers, FH Westküste ; Johann Wiesböck, ELEKTRONIKPRAXIS (Hrsg.) : HighSys '99, pp. 352-359, 1999 (High Reliable Hard- and Software Systems Sindelfingen September '99).

2010

  • Heiko Hinkelmann and Peter Zipf and Manfred Glesner:
    Dynamically Reconfigurable Systems for Wireless Sensor Networks,
    in Platzner, Marco; Teich, Jürgen; Wehn, Norbert (Eds.): Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications, Springer Verlag, 1st Edition., 2010, XXV, pp. 315-334. ISBN 978-90-481-3484-7 

2006

  • Manfred Glesner, Oliver Soffke, Peter Zipf:
    Hardware Architectures for the Evolution of Cellular Automata Functionality,
    in Izzet Cem Göknar and Levent Sevgi (Eds.): Complex Computing-Networks: Brain-like and Wave-oriented Electrodynamic Algorithms, 104 | Springer Proceedings in Physics, chap. 28, pp. 257-266, July 5, 2006. ISBN 3540306358.

2004

  • Peter Zipf and Manfred Glesner:
    Systems on a Chip
    in Maurizio Valle (Ed.): Smart Adaptive Systems on Silicon, chap. 2, pp. 17-32, Kluwer Academic Publisher, 2004. ISBN 1-4020-2743-5.

2003

  • M. Glesner, H. Eveking, L.S. Indrusiak, R. Reis, V. Mooney, P. Zipf (Eds.):
    VLSI-SoC 2003
    IFIP WG 10.5 Conference on Very Large Scale Integration of System-on-Chip, December 1-3, 2003, Darmstadt, Germany. ISBN 3-901882-17-0.

2002

2014

  • Konrad Möller, Martin Kumm, Peter Zipf, Kerstin Groß, Dieter Lens, and Harald Klingbeil: FPGA Based Tunable Digital Filtering for Closed Loop RF Control in Synchrotrons, In: Scientific Report 2013, vol. 2014, Darmstadt: GSI Helmholtzzentrum für Schwerionenforschung, 2014 (preprint, copyright GSI)

2011

  • E. Bayer, P. Zipf, G. Schreiber, A. Klaus:
    Barrier Bucket Low-Level RF Development,
    GSI Scientific Report 2011, GSI Report 2012-1, p. 322, PHN-ACC-RD-35

2009

  • C Spies, P Zipf, A Guntoro, P Surapong, M Glesner, H Klingbeil:
    A model-based development approach for multi-cavity RF control systems,
    GSI Scientific Report, 2009, GSI Report 2010-1

2006

  • P. Zipf, A. Guntoro, M. Glesner, and H. Klingbeil:
    Reconfigurable Computing Systems for Digital RF Closed-Loop Controls,
    p. 65, GSI Scientific Report 2006, GSI Report 2007-1, June 2007, FAIR-ACCELERATORS-21
  • M. Kumm und P Zipf, Verfahren zum Multiplizieren zweier Binärzahlen mit einer programmierbaren Logikanordnung und zur Durchführung des Verfahrens geeignete Logikanordnung, 2015, DPMA
  • M. Kumm und P Zipf, Verfahren zum Berechnen von Funktionswerten mit einer Logikanordnung und zur Durchführung des Verfahrens geeignete Logikanordnung, submitted 2017