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Prof. Dr.-Ing. Peter Zipf

Head of department

Zipf, Peter

Telephone: +49 561 804-6379
Fax: +49 561 804-6373
Email: zipf[at]uni-kassel[dot]de

Location: Wilhelmshöher Allee 73
34121 Kassel

Room: WA-altes Gebäude (WA 73), R 0329

Sittel, P., Kumm, M., Möller, K., Hardieck, M., Zipf, P., 2017. High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits, in: Universität Bremen (Hrsg.), 20. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). Shaker Verlag, Herzogenrath, S. 103–113.
Möller, K., Kumm, M., Zipf, P., Müller, C.-F., 2015. Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. FPGAs for Software Programmers 2015, 1–8.
Möller, K., Kumm, M., Barschtipan, B., Zipf, P., 2014. Dynamically Reconfigurable Constant Multiplication on FPGAs, in: Ruf, J., Allmendinger, D., Michel, M. (Hrsg.), Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). Cuvillier Verlag, Göttingen, S. 159–169.
Möller, K., Kumm, M., Kleinlein, M., Zipf, P., 2014. Pipelined reconfigurable multiplication with constants on FPGAs, in: IEEE (Hrsg.), Field Programmable Logic and Applications (FPL), 2014 24th International Conference on. IEEE, New York, S. 1–6. https://doi.org/10.1109/FPL.2014.6927466
Kumm, M., Klingbeil, H., Möller, K., Zipf, P., Groß, K., Lens, D., 2014. FPGA Based Tunable Digital Filtering for Closed Loop RF Control in Synchrotrons, in: Große, K. (Hrsg.), Scientific Report 2013. GSI Helmholtzzentrum für Schwerionenforschung, Darmstadt, S. 331–332.
Kumm, M., Fanghänel, D., Möller, K., Zipf, P., Meyer-Baese, U., 2013. FIR filter optimization for video processing on FPGAs. EURASIP Journal on Advances in Signal Processing 2013, 111–46. https://doi.org/10.1186/1687-6180-2013-111
Möller, K., Kumm, M., Zipf, P., 2013. Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. Circuits and Systems (ISCAS), 2013 IEEE International Symposium on 2054–2057. https://doi.org/10.1109/ISCAS.2013.6572276
Möller, K., Kumm, M., Zipf, P., 2013. Reconfigurable FIR filter using distributed arithmetic on FPGAs. Circuits and Systems (ISCAS), 2013 IEEE International Symposium on 2058–2061. https://doi.org/10.1109/ISCAS.2013.6572277
Möller, K., Kumm, M., Zipf, P., 2013. Dynamically reconfigurable FIR filter architectures with fast reconfiguration, in: IEEE (Hrsg.), 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, New York, S. 1–8. https://doi.org/10.1109/ReCoSoC.2013.6581517
Kumm, M., Liebisch, K., Zipf, P., 2012. Reduced complexity single and multiple constant multiplication in floating point precision, in: IEEE (Hrsg.), 22nd International Conference on Field Programmable Logic and Applications (FPL). IEEE, S. 255–261. https://doi.org/10.1109/FPL.2012.6339190
Kumm, M., Zipf, P., Faust, M., Chang, C.-H., 2012. Pipelined adder graph optimization for high speed multiple constant multiplication, in: IEEE (Hrsg.), 2012 IEEE International Symposium on Circuits and Systems. IEEE, S. 49–52. https://doi.org/10.1109/ISCAS.2012.6272072
Kumm, M., Zipf, P., 2012. Hybrid multiple constant multiplication for FPGAs, in: IEEE (Hrsg.), 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012). IEEE, S. 556–559. https://doi.org/10.1109/ICECS.2012.6463686
Kunz, M., Kumm, M., Heide, M., Zipf, P., 2012. Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system, in: IEEE (Hrsg.), 22nd International Conference on Field Programmable Logic and Applications (FPL). IEEE, S. 591–594. https://doi.org/10.1109/FPL.2012.6339214
Bayer, E., Zipf, P., Traxler, M., 2011. A multichannel high-resolution (<5 ps RMS between two channels) Time-to-Digital Converter (TDC) implemented in a field programmable gate array (FPGA), in: IEEE (Hrsg.), 2011 IEEE Nuclear Science Symposium Conference Record. IEEE, S. 876–879. https://doi.org/10.1109/NSSMIC.2011.6154560
Kumm, M., Zipf, P., 2011. High speed low complexity FPGA-based FIR filters using pipelined adder graphs, in: IEEE (Hrsg.), 2011 International Conference on Field-Programmable Technology. IEEE, S. 1–4. https://doi.org/10.1109/FPT.2011.6132698