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Nicolai Fiege (M. Sc.)

Research assistant

Location
Wilhelmshöher Allee 73
34121 Kassel
Room
WA-altes Gebäude (WA 73), without room specification
Telephone
+49 561 804-6188
Email
Consultation Hours

by appointment by mail.

Room number  (Nicolai Fiege (M. Sc.))

I am sitting in room 0339 (entrance via room 0335).

Vita  (Nicolai Fiege (M. Sc.))

  • Since 2021: PhD student, University of Kassel
  • 2018 - 2021: Master Electrical Engineering, University of Kassel (Thesis: "Throughput-Optimal Modulo Scheduling with Rational Initiation Intervals for Computer-Aided Hardware Design", VDE Förderpreis für herausragende Studienleistungen)
  • 2014 - 2018: Bachelor Electrical Engineering, University of Kassel (Thesis: "Automatic VHDL-Code Generation of Convolutional Neural Networks for System-on-Chips")

Publications  (Nicolai Fiege (M. Sc.))

  • N. Fiege, M. Kumm and P. Zipf, "Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability," in  IEEETransactions on Circuits and Systems I: Regular Papers, vol. 71, no. 1, pp. 249-261, Jan. 2024, doi: 10.1109/TCSI.2023.3327814.
  • N. Fiege and P. Zipf, 'BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining', ACM Trans. Reconfigurable Technol. Syst., vol. 16, no. 3, p. 49:1-49:32, Jul. 2023, doi: 10.1145/3599972.
  • N. Fiege, P. Sittel, and P. Zipf, 'Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis', in 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), Aug. 2022, pp. 262-269. doi: 10.1109/FPL57034.2022.00047.
  • N. Fiege, P. Sittel, and P. Zipf, 'Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals', in 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), Aug. 2022, pp. 322-326. doi: 10.1109/FPL57034.2022.00056.
  • N. Fiege, P. Sittel, and P. Zipf, 'Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling', in 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2022, pp. 1-2. doi: 10.1109/FCCM53951.2022.9786117.
  • P. Sittel, N. Fiege, J. Wickerson, and P. Zipf, 'Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 3, pp. 614-627, Mar. 2022, doi: 10.1109/TCAD.2021.3060320.
  • P. Sittel, N. Fiege, M. Kumm, and P. Zipf, 'Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling', in 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Dec. 2019, pp. 1-8. doi: 10.1109/ReConFig48160.2019.8994768

Pre-Prints  (Nicolai Fiege (M. Sc.))

Open works  (Nicolai Fiege (M. Sc.))

I am interested in various topics of circuit optimization (especially high-level synthesis & arithmetic) but also in general optimization "no matter what". Currently the following work is available:

  • Incremental system of difference constraints solver according to literature template
  • Extension: API for Boolean Satisfiability Solver
  • Comparison of different implementation methods for FIR filters on FPGAs
  • Modulo scheduling algorithm according to literature template
  • Random graph generation based on real models
  • Re-implementation of a method for optimal word width selection using integer linear programming

  • Design of optimized standard cells/switching networks at gate level

  • Standard cell optimization at transistor level in CMOS technology

  • ASIC implementation and evaluation of our arithmetic circuits

  • Power loss estimation of switching networks by means of entropy calculation

  • Automated finding of almost identical subcircuits

Almost all of the above work can be completed both as a project and as a thesis. Please contact us by e-mail if you are interested. Alternatively, you are also welcome to come to me with your own (thematically suitable) topic suggestions. In any case, please write in your e-mail 1) what type of work you are looking for (project or thesis), 2) what topic you are interested in, 3) what previous knowledge you have and 4) what you are studying.

Work in progress  (Nicolai Fiege (M. Sc.))

  • Achmad Luthfi Nugroho "Optimal Matrix Multiplication with Integer Linear Programming" (Project)
  • Jan Philipp Rauwolf "FPGA-accelerated vibration localization" (Bachelor)
  • Oliver Preuß & Alexander Rebbe "Construction and commissioning of a 3D-printed robot arm" (Project)
  • Julian Werner "Arithmetic operator library incl. C++ API & porting of Origami HLS to Python" (Project)
  • Florian Zimmermann "Design and implementation of an FPGA-based GPU with Risc-V cores" (Bachelor)

Supervised work  (Nicolai Fiege (M. Sc.))

2024

  • Achmad Luthfi Nugroho "Implementation of a method for optimized FIR filter implementation" (Bachelor)
  • Guanyu Qiu "Accelerating Boolean Satisfiability Solvers on FPGAs" (Master)
  • Florian Zimmermann "FPGA-Accelerated Rendering of 3D Scenes" (Project)
  • Philipp Schenk, "Non-Iterative Modulo Scheduling" (Bachelor)
  • Michel Schäfer, Timo Busch "Metrological determination of the coffee roasting wheel" (Project)
  • Christoph Becker "Optimal Constant Matrix Multiplication with Boolean Satisfiability" (Bachelor)

2023

  • Philipp Schenk "Generic C++ API for Boolean Satisfiability Solvers" (Project)
  • Jan Philipp Rauwolf "Triangulation of vibrations" (Project)
  • Lucas Scheerer "Functionality of SAT solver algorithms" (Project)
  • Christoph Becker "Heuristic Modulo Scheduling with Rational IIs" (Project)
  • Benjamin Lagershausen-Keßler "SMT-based modulo scheduling" (Bachelor)

2022

  • Benjamin Lagershausen-Keßler "Implementation of the Ethernet interface of the PYNQ board" (Project)
  • Guanyu Qiu "Design and Implementation of a Signal Generator" (Project)

Courses  (Nicolai Fiege (M. Sc.))

Winter semester 2024/25

  • VHDL practical course

Summer semester 2024

  • VHDL course/circuit design with HDLs

Winter semester 2023/24

  • Digital Logic Exercise
  • VHDL practical course (canceled due to lack of participants)

Summer semester 2023

  • VHDL course/circuit design with HDLs

Winter semester 2022/23

  • Digital logic exercise
  • VHDL practical course
  • Embedded Systems Practical Course

Summer semester 2022

  • VHDL course/circuit design with HDLs

Winter semester 2021/22

  • Digital Logic Exercise
  • VHDL practical course

Summer semester 2021

  • VHDL course/circuit design with HDLs

Notes on project & final theses  (Nicolai Fiege (M. Sc.))

We are often asked for "instructions" for project and final papers. Here is a small collection of information on how to write a good thesis:

  • You can find general tips on the structure of written theses on the Computer Science course page: https: //www.uni-kassel.de/eecs/studium/bachelor/informatik#c1006263 (PDF "Ratgeber Abschlussarbeit" by Prof. Wegner)
  • Andrey Churkin has a nice video on how to produce sensible illustrations: https: //www.youtube.com/watch?v=i-HAjex6VtM (the video refers to scientific publications, but the information can be applied just as well to student papers!)
  • LaTeX templates from our department are available on request by e-mail (please do not use Word...!)
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