Selected chapters of computer architecture

Learning Objectives:

• In-depth knowledge of digital circuit design.
• VHDL design
• Implementation of simple architectures on FPGA level

Learning inhold:
Design of computer architectures, VHDL implementations, FPGA programming

Previous knowledge:
Digital logic, computer architecture LV from 5th semester onwards

Course number: FB16-6804

Location and time:
Wednesdays: 9:00 am to 5:00 pm (2+2 SWS, total of 3 full hours of prereq time weekly, more specific times will be announced after the meeting date!)
Room: 2107 (MSP lab of the department).

The preconference meeting for the lecture will be held on 10/21/2015 at 10:00 am in room 2107! 

Lecturer:
Prof. Dr.-Ing. habil. Josef Börcsök
Dr. -Ing. Ali Hayek

Scope:
4 SWS resp. 6 CP

Contact:
Email to Dr. Ali Hayek

Written exam:
Oral or written exam, depending on the number of participants.
Dates will be given by arrangement.