E-learning with tablet computers and smartphones

Short info: We are investigating how to support students and teachers in the daily routine of lecturing, practicing and learning and how to provide concrete help for learning. For this purpose, we are developing a client-server system with apps as clients. The implementation is done on iOS.

Student work: You will develop iOS (iPad, iPhone) apps and connectivity to server software. If you are interested, we also support work with Android. Just contact us to clarify details!

Short info: For a particle accelerator near Darmstadt we are working on FPGA circuits for beam control. These circuits must meet extreme timing constraints (in the nanosecond range).

Student work: Interesting for e-technicians and computer scientists! You develop FPGA circuits (Bachelor/Master theses) with FPGAs at the limit of what is possible. Just contact us if you are interested!

More information about the project: here

The e-learning software to be created as part of the project(for iPad and iPhone and Android) has the objective of supporting students and teachers in the daily routine of lectures, exercises and learning. Beyond that, however, the student-facing software is to be used in such a way that specific support and encouragement (advising) of the individual student is achieved, also in the context of self-finding small learning groups.

The possibilities of modern tablet computers and smartphones are to be used to provide computer-based teaching and learning support. The main aim is to directly accompany lecture-based teaching, associated exercises and supplementary materials by providing interaction within lectures and immediate feedback of data. Together with a downstream analysis, deficits of the students can be recognized and problem areas within individual courses can be identified. Based on this, long-term improvements of the teaching material can be made on the one hand, and short-term remedies such as additional tutorials or simply repetition of material can be offered on the other. The necessary data is available directly after each course and in some cases already during the course.

On the student side, highly individualized learning advice and progress analysis based on all available data is offered in addition. Through an interaction of the end devices firmly assigned to the individual students among themselves, contacts for and between learning groups can then also be suggested and accompanied.

The aim of the project is thus to provide a corresponding software environment for lecturers and students and to adapt it optimally to the application area "Lecture". A main point of view is that the so far proven way of conducting such events does not have to be changed radically, but that the additional possibilities can be integrated in a complementary way and in no steps according to the needs. Other types of events, such as seminars, can be investigated during the project to determine which software enhancements would be necessary to support them. The project is to be didactically accompanied in cooperation with the SCL and the pursued concept is to be constantly improved on the basis of this consultation and on the basis of interim results. 

Highly specialized systems are required for resource-critical applications in order to achieve the required performance with simultaneous energy efficiency. Single-chip systems, so-called system-on-chips (SoC), are an implementation option. Reconfigurable circuits (the best-known representatives of these are FPGAs) not only offer the possibility of realizing such systems without the design and manufacture of a further specialized VLSI chip (ASIC) due to their now sufficiently large gate capacity, but also permit a dynamic change of the implemented functionality during operation. This allows a temporal structural adaptation of the hardware to the requirements, which can increase both performance and energy efficiency. Such systems are then called System-on-Programmable-Chip (SoPC).

The ability to reconfigure is purchased with additional hardware expenditure, which initially brings disadvantages in terms of area, performance and energy efficiency. However, these can be partially compensated for by clever application of dynamic partial reconfiguration (replacement of partial functionality at runtime). Especially critical is the implementation of the reconfiguration process.

Our research addresses the possibilities of this compensation. FPGA-based implementations as well as newly designed reconfiguration structures are investigated and compared. Among other things, we are concerned with the question of whether dynamic reconfiguration must use the programmability of the underlying hardware to be efficient, or whether meta-reconfiguration is sufficient, i.e., can be abstracted from the hardware. Our applications are in the area of real-time data processing in embedded hardware systems. To this end, we have been working on wireless sensor network nodes for some time and are just starting to build camera data processing in addition. In the future, we also plan to add flight state data processing as part of the UniKOPTER project. In all cases, attempts are being made to achieve better system characteristics through hardware realizations of the required algorithms.

Theses are available for students in this research area (Bachelor, Master, D1/D2). Previous experience in digital circuit design, hardware description languages (VHDL or Verilog) or microprocessor systems is advantageous.

FAIR is a new, international accelerator facility for research with antiprotons and ions, which will be built in the next years by GSI (Gesellschaft für Schwerionenforschung) near Darmstadt (click here for the FAIR website of GSI). Within the FAIR project, barrier bucket systems for a flexible particle beam manipulation are planned, for which a control electronics, a barrier bucket low-lever radio frequency system (BB-LLRF), is needed. 

Our project in collaboration with GSI is focused on the realization of this BB-LLRF system. Our developments shall be suitable for implementation on an FPGA platform. Furthermore, the real-time data supply and the connection to the control system related to the BB-LLRF system shall be worked on. FPGA-based subsystems are already used extensively in the field of RF systems at SIS100 and for the FAIR project, so previous experience can be drawn upon for this. New in the context of this project is the time resolution below 1 ns. This has to be achieved within the FPGA, which requires special investigations and designs. In this context, possibilities for continuous signal phase alignment based on an external reference will probably also have to be investigated. The main objectives of the planned work are 

• the selection of a suitable signal synthesis method for the barrier pulses, 
• the implementation of the synthesis procedure on an FPGA system at GSI, 
• the investigation and realization of a calibration and adjustment procedure for the precision timing of the signal synthesis, 
• the construction of an interface to the control system and the optical trigger distribution for the ring-to-ring transfer. 

The project thus includes all components and implementations necessary for a prototypical realization and system integration of the BB-LLRF system. Accordingly, a prototype installed there is to be set up already during the project duration in cooperation with GSI, on which the functionality of the individual results can be tested in experimental operation and which will enable a complete demonstration of the project results at the end.

For our students: Within the scope of this project, you can collaborate on FPGA-based circuit designs or perform investigations on given circuits.